Preliminary Program

Tentative 2026 schedule — subject to change.

8:45-9:00am	Welcome
9:00-10:00am	Keynote 1: Carole-Jean Wu — “A Journey Towards Sustainable AI”
10:00-10:30am	Coffee Break
10:30-11:30am	Lightning Talks
11:30am-12:00pm	Poster Session I
12:00-1:30pm	Lunch + Round-table Mentoring (venue permitting)
1:30-1:45pm	Presentation of CaSA
1:45-2:30pm	Keynote 2: Josep Torrellas — “Some Thoughts on Leading a Productive Graduate School Career” (30 min talk + 15 min Q&A)
2:30-3:30pm	Poster Session II
3:30-4:00pm	Coffee Break
4:00-5:30pm	Panel Discussion: Demystifying Grad School
5:30pm	Closing Remarks

Accepted Papers

• iGuardian: Invisible Speculation for the Instruction Side
  Anushka Subramanian (The University of Texas at Austin); Ziang Tian (The University of Texas at Austin); Lizy John (The University of Texas at Austin)
• Synthesizing Execution Contracts from RTL for Formally Verified Hardware Side-Channel Defenses
  Xiaofu Li (Stanford University); William Zhu (Stanford University); Samantha Archer (Stanford University); Caroline Trippel (Stanford University)
• An Empirical Framework for Identifying Instruction Fusion Candidates
  Michael Shires (University of Virginia); Logan Moody (University of Virginia); Ashish Venkat (University of Virginia)
• Interactive Design Space Exploration for Sparse Accelerators
  Evan Williams (Carnegie Mellon University); Justin Lubin (University of California, Berkeley); Rubens Lacouture (Stanford University); Olivia Hsu (Stanford University/Carnegie Mellon University)
• Beyond the Black Box: Automated Per-Component Equation Modeling to assist CPU Performance Modeling
  Krishbin Paudel (University of South Florida); Santosh Pandey (University of South Florida)
• Native ML Watermarking in Approximate DRAM
  Jack Chandler (Virginia Tech); Wenjie Xiong (Virginia Tech)
• A Register Tracking Scheme for the Gem5 Simulator
  Thomas Bakewell (The University of Virginia); Logan Moody (The University of Virginia); Ashish Venkat (The University of Virginia)
• Asymmetric Gates for Distributed Quantum Computing
  Haoyan Lou (Rutgers University); Winston Li (Rutgers University); Pooja Kedia (Rutgers University); Enhyeok Jang (Yonsei University); Won Woo Ro (Yonsei University); Alexei Ashikhmin (Nokia Bell Labs); Yipeng Huang (Rutgers University)
• Toward Efficient Humanoid Control with Hardware-Algorithm Codesign for Nonlinear MPC
  Yubin Lee (KAIST); Jiyong Jung (KAIST); Sangin Jeon (KAIST); Jongse Park (KAIST)
• Automated Discovery and Offloading of Acceleratable Code in Datacenters
  Joshua Kim (University of Texas at Austin); Peizhe Liu (University of Texas at Austin); Chaojie Zhang (Microsoft); Íñigo Goiri (Microsoft); Christopher J. Rossbach (UT Austin and Microsoft); Jovan Stojkovic (UT Austin and Meta)
• Portable Dynamic Tiling for Sparse Tensor Applications
  Sai Gautham Ravipati (Stanford University); Fredrik Kjolstad (Stanford University); Priyanka Raina (Stanford University); Olivia Hsu (Stanford University)
• Agentic AI Framework for Synthesizing Microarchitecture-Faithful Datacenter Benchmarks
  Alan Andrade (UT Austin); Petar Acimovic (University of Cincinnati); Wei Su (Meta); Suyash Mahar (Meta); Apostolos Kokolis (Meta); Abhishek Dhanotia (Meta); Jovan Stojkovic (UT Austin and Meta)
• Hot Superpage Buffers to Improve Graph Workload Performance
  Yuchen He (University of California, Santa Barbara); Jonathan Balkind (UC Santa Barbara); Juan Luis Aragón (University of Murcia)
• Scaling SupermarQ to GPUs and Modern Quantum Machines
  Rena Feng (Princeton University); Vivian Zhang (Duke University); Coco Gong (Princeton University); Keqin Yan (Duke University); Bahaa Harraz (Duke University); Yichao Yu (Duke University); Crystal Noel (Duke University); Alexander Kozhanov (Duke University); Christopher Monroe (Duke University); Margaret Martonosi (Princeton University)
• Store or Recompute? Characterizing the Carbon Tradeoff of KV Cache Retention in LLM Inference
  Abnash Bassi (Carnegie Mellon University); Jaylen Wang (Carnegie Mellon University); Fiodar Kazhamiaka (Microsoft); Daniel S. Berger (Microsoft); Akshitha Sriraman (Carnegie Mellon University)
• 3D-CoolPress: An Edge Processing Architecture Using In-Memory-Compression Engines to Enhance Off-Chip Memory Bandwidth Considering Thermal Constraints in 3D Integration
  Cheng Peng (Tsinghua University); Liu He (Tsinghua University); Yujin Wang (Tsinghua University); Luchang Lei (Tsinghua University); Hongyang Jia (Tsinghua University)
• Márohu: Scalable CGRA Mapping through Reinforcement Learning a Hierarchical Pointer Network
  Alexander Coppens (University of Maryland, College Park); Bahar Asgari (University of Maryland, College Park)
• APT: Architecture Performance across Topologies
  Dongwhee Kim (University of Texas at Austin); Poulami Das (University of Texas at Austin)
• SimSpect: Automated litmus testing for simulated Spectre defenses
  Anna Eaton (Stanford University); Caroline Trippel (Stanford University)
• Bounce and Break: Ciphertext Side-Channels in ML Workloads on GPU Confidential Computing
  Eunseong Park (Virginia Tech); Wenjie Xiong (Virginia Tech)
• Heterogeneous Pipelined Execution for Diffusion Models on Mobile SoCs
  Lakshmanan Lakshmanan (University of Edinburgh)
• Agentic Architect: An Agentic Framework for CPU Microarchitecture Design Optimization
  Alexander Blasberg (Carnegie Mellon University); Vasilis Kypriotis (Carnegie Mellon University); Dimitrios Skarlatos (Carnegie Mellon University)
• A case study of High Bandwidth Flash
  Kian Mahmoodi (Cornell University)
• Inductive Invariants for Ordering Properties
  Yicheng Qian (Stanford University); Caroline Trippel (Stanford University)
• HyPA: Enabling Development of Scalable Applications on Hybrid Digital-Analog Architectures
  Jacob Flores (Sandia National Laboratories)
• Breaking the Address Translation Wall with Accordion Page Tables
  Nevena Stojkovic (MIT); Dimitrios Skarlatos (Carnegie Mellon University)
• CMOS Evaluation of Primitives for a Novel Directed Dataflow Architecture
  A. Tayseer Aly (Georgia Institute of Technology); Pulkit Gupta (Georgia Institute of Technology); Thomas M. Conte (Georgia Institute of Technology)
• Axolotl: Reducing Embodied Carbon Through Error-Tolerance and Reliability
  Elise Song (University of Wisconsin–Madison); Zhewen Pan (University of Wisconsin–Madison); Joshua San Miguel (University of Wisconsin–Madison)
• Specifying Hardware Communication as Programs
  Ernest Ng (Cornell University); Nikil Shyamsunder (Cornell University); Francis Pham (Cornell University); Adrian Sampson (Cornell University); Kevin Laeufer (Cornell University)
• IO All Around Accelerators: Addressing the Data-Delivery Wall in the AI Era
  Ethan Berkley (Cornell University)
• Understanding Unified System Memory in Emerging Superchips
  Mohammad Sonji (University of Virginia)
• Characterizing Microarchitectural Behavior of LLM-Generated Code
  Kelly Farran (University of Virginia); Logan Moody (University of Virginia); Ashish Venkat (University of Virginia)

SUBMIT

Eligibility

Applicants must be either (a) research-active undergraduate students aiming for graduate school, or (b) graduate students (Masters and/or PhD) in computer architecture and related fields who have completed less than 3 years of graduate school at the time of the workshop. A note from the student’s research advisor attesting this is required as part of the submission.

Eligible students are invited to submit their early stage or on-going work to this workshop. Submitted work should not have been presented as part of a prior ACM/IEEE conference.

Note: This workshop is not a venue for publication and there will be no formal proceedings.

Topics of Interest

The workshop invites papers from all areas of computer architecture, broadly defined. Topics of interest include, but not limited to:

• Datacenter systems
• Hardware acceleration
• Memory hierarchy
• Virtualization
• Security
• Microarchitecture
• GPUs
• Parallel architectures
• Emerging technologies

Submission Guidelines

The goal of this workshop is to help students think about a problem/idea in an holistic manner and communicate your ideas to the wider community, so that we can provide some valuable early-stage feedback. To this end, we encourage you to cover the following aspects in your submission:

• Scope of problem/idea: Provide clear context for and scope of the problem(s) or idea(s) you intend to work on. This will likely form the basis of the introduction/background sections of your future work(s).
• Solution: Provide an overview of the design and implementation aspects of your solution(s) to the problem(s) described above. Given this is on-going work, focus more on providing breadth than depth. For example, beside describing the design of your idea, enlist the various system aspects which your proposed solutions will affect (e.g. does your proposed solution affect coherence protocols?) and that if you plan to discuss these effects in your future submission(s).
• Evaluation methodology: Discuss the evaluation methodology you plan to adopt to test the efficacy of your ideas. For example, the workloads that you plan to use, the tools you’ll employ (e.g., architectural simulator, real world experiments, FPGA prototypes), etc.
• Related work: This can be the traditional related work section. Please specify if you plan to quantitatively compare against some prior work.

Submission Details

• Submissions must be PDF files, in 2-column, single-spaced, 10pt format, at most 2 pages long, not including references.
• Submissions are double-blind. Please do not have any author identifying information in the paper submitted.
• Please have your research advisor send the workshop organizers an email with the following subject line “<Your name> meets YArch’26 eligibility requirements” to youngarchitectw@gmail.com.
• Submission site: https://yarch26.hotcrp.com

Declaring Conflicts

When registering a submission, all its co-authors must provide information about conflicts with the YArch’26 program committee members. You are conflicted with a member if:

1. you are currently employed at the same institution, have been previously employed at the same institution within the past two years (2024 or later), or are going to begin employment at the same institution;
2. you have a past or present association as thesis advisor or advisee (no time limit);
3. you have collaborated on a project, publication, grant proposal, or editorship within the past two years (2024 or later);
4. or, you have spouse or first-degree relative relations.

Funding FAQ

1. We aim to fund one person per paper (the presenter/first author).
2. Depending on available funding we may only cover partial costs.
3. We aim to fund the presenters from all accepted papers.

Sponsors:

Interested in sponsoring YArch'26? See our sponsorship page for details.